Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure

ABSTRACT

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and is a Divisional application ofU.S. patent application Ser. No. 14/940,785, filed Nov. 13, 2015, whichclaims priority to and is a Divisional application of U.S. patentapplication Ser. No. 13/169,348, filed Jun. 27, 2011, now U.S. Pat. No.9,202,813, which claims the benefit of priority to Korean PatentApplication No. 10-2010-0063871, filed on Jul. 2, 2010, in the KoreanIntellectual Property Office, the disclosure of each of which isincorporated herein in its entirety by reference.

BACKGROUND

The disclosed embodiments relate to an electrode structure, a method offabricating the electrode structure, and a semiconductor deviceincluding the electrode structure.

As semiconductor devices become highly integrated, electrode structuresincluding the semiconductor devices benefit from maintaining lowresistances. The electrode structures should be easily fabricatedthrough a process of fabricating the semiconductor devices. It isdesirable for the electrode structures including the semiconductordevices to have a low reactivity with other material layers, forexample, polysilicon layers or metal layers. In addition, it isdesirable to prevent impurities contained in the electrode structuresincluding the semiconductor devices from diffusing over to semiconductorsubstrates.

SUMMARY

The disclosed embodiments provide an electrode structure having a lowresistance and capable of preventing impurities contained therein fromdiffusing, and further capable of inhibiting reactivity with anothermaterial layer.

The disclosed embodiments also provide a method of fabricating anelectrode structure capable of increasing a manufacturing process'degrees of freedom.

The disclosed embodiments additionally provide a semiconductor deviceusing the above-described electrode structure.

According to one embodiment, there is provided an electrode structureincluding: a first polysilicon layer doped with resistance adjustmentimpurities; and a second polysilicon layer for adjusting grains, formedon the first polysilicon layer doped with the resistance adjustmentimpurities and additionally doped with grain adjustment impurities. Theelectrode structure further includes an ohmic metal layer formed on thefirst and second polysilicon layers; a barrier metal layer formed on theohmic metal layer; and a metal layer formed on the barrier metal layer.

The second polysilicon layer may be disposed between the firstpolysilicon layer and the ohmic metal layer. The second polysiliconlayer may be uniformly formed on the first polysilicon layer. The secondpolysilicon layer may be formed in a specific level of the firstpolysilicon layer. The second polysilicon layer may be uniformly formedin the first polysilicon layer.

In one embodiment, the second polysilicon layer is formed in the entirefirst polysilicon layer so that the second polysilicon layer and thefirst polysilicon layer are formed as a single polysilicon layer. Thegrain adjustment impurities doped in the second polysilicon layer may beone or more of carbon, nitrogen, and oxygen. The ohmic metal layer maybe a metal silicide layer.

According to another aspect of the disclosed embodiments, there isprovided a method of fabricating an electrode structure, the methodincluding: forming a polysilicon layer doped with resistance adjustmentimpurities on a semiconductor substrate, the polysilicon layer includinga first polysilicon layer including the resistance adjustment impuritiesas the only impurities; forming a second polysilicon layer for adjustinggrains and doped with grain adjustment impurities in the polysiliconlayer doped with the resistance adjustment impurities; forming an ohmicmetal layer on the second polysilicon layer; forming a barrier metallayer on the ohmic metal layer; and forming a metal layer on the barriermetal layer.

The second polysilicon layer may be formed on the polysilicon layer byin-situ depositing a precursor including one or more of carbon,nitrogen, and oxygen. The second polysilicon layer may be formed bydoping one or more of carbon, nitrogen, and oxygen through an epitaxialgrowth process.

According to another aspect of the disclosed embodiments, there isprovided a semiconductor device including: a semiconductor substrateincluding a p-type metal-oxide-semiconductor (PMOS) region and an n-typemetal-oxide-semiconductor (NMOS) region; a first gate stack formed onthe PMOS region of the semiconductor substrate and comprising a firstelectrode structure; and a second gate stack formed on the NMOS regionof the semiconductor substrate and comprising a second electrodestructure.

Each of the first electrode structure and the second electrode structureincludes: a polysilicon layer doped with resistance adjustmentimpurities; a polysilicon layer for adjusting grains formed in thepolysilicon layer doped with the resistance adjustment impurities anddoped with grain adjustment impurities; an ohmic metal layer formed onthe polysilicon layer including the polysilicon layer for adjusting thegrain; a barrier metal layer formed on the ohmic metal layer; and ametal layer formed on the barrier metal layer, wherein the existence ofthe polysilicon layer for adjusting the grain results in a reduceddifference in the thickness between the ohmic metal layer of the firstelectrode structure and the ohmic metal layer of the second electrodestructure.

The first gate stack may include a first gate insulation layer formed onthe semiconductor substrate, a first polysilicon layer formed on thefirst gate insulation layer and doped with P type impurities, and afirst polysilicon layer for adjusting the grain, formed in the firstpolysilicon layer doped with the P type impurities, wherein the firstelectrode structure comprises a first ohmic metal layer formed on thefirst polysilicon layer for adjusting the grain.

The P type impurities may be inhibited from diffusing over to thesemiconductor substrate due to the first polysilicon layer for adjustingthe grain.

The second gate stack may include a second gate insulation layer formedon the semiconductor substrate, a second polysilicon layer formed on thesecond gate insulation layer and doped with N type impurities, and asecond polysilicon layer for adjusting the grain formed in the secondpolysilicon layer, wherein a second electrode structure comprises asecond ohmic metal layer formed on the second polysilicon layer foradjusting the grain.

The thickness of the second ohmic metal layer included in the secondelectrode structure may be reduced due to the second polysilicon layerfor adjusting the grain. The first ohmic metal layer and the secondohmic metal layer may be silicide layers.

The polysilicon layer for adjusting the grain may be doped with one ormore of carbon, nitrogen, and oxygen. The first electrode structure andthe second electrode structure may be gate electrodes or word lines.

According to another embodiment, there is provided a semiconductordevice including: a plurality of gate stacks formed on a semiconductorsubstrate; an impurity region formed on the semiconductor substratebetween the plurality of gate stacks; and a pad electrode formed betweenthe plurality of gate stacks on the impurity regions and comprising anelectrode structure.

The electrode structure included in the pad electrode may include: afirst polysilicon layer; a second polysilicon layer, formed in the firstpolysilicon layer and doped with grain adjustment impurities; an ohmicmetal layer formed on the second polysilicon layer; a barrier metallayer formed on the ohmic metal layer; and a metal layer formed on thebarrier metal layer.

Each of the plurality of gate stacks may include a gate insulationlayer, a gate electrode, and a gate cap layer, the gate insulation layerbeing formed in a recess channel trench formed by etching thesemiconductor substrate, and the gate electrode being formed on the gateinsulation layer formed in the recess channel trench and on thesemiconductor substrate.

The second polysilicon layer included in the electrode structureincluded in the pad electrode may be disposed between the ohmic metallayer and a portion of the first polysilicon layer that includesimpurities consisting only of the resistance adjustment impurities. Theohmic metal layer may be a metal silicide layer. The second polysiliconlayer included in the electrode structure included in the pad electrodemay be formed in a specific level of the first polysilicon layer. Thesecond polysilicon layer included in the electrode structure included inthe pad electrode may be formed in the entire of the first polysiliconlayer.

Each of the plurality of gate stacks may include a gate insulationlayer, a gate electrode, and a gate cap layer, the electrode structurecomprising a polysilicon layer doped with resistance adjustmentimpurities; a polysilicon layer for adjusting grains, formed in thepolysilicon layer doped with the resistance adjustment impurities anddoped with grain adjustment impurities; an ohmic metal layer formed onthe polysilicon layer including the polysilicon layer for adjusting thegrain; a barrier metal layer formed on the ohmic metal layer; and ametal layer formed on the barrier metal layer.

According to another embodiment, there is provided a semiconductordevice including: a plurality of gate stacks formed on a semiconductorsubstrate and acting as a plurality of word lines; an impurity regionformed on the semiconductor substrate between the plurality of gatestacks; a direct contact (DC) pad electrode and a burying contact (BC)pad electrode formed between the plurality of gate stacks on theimpurity regions and comprising an electrode structure; and bit linesand capacitors connected to the DC pad electrode and the BC padelectrode, respectively.

The electrode structure included in the DC pad electrode and the BC padelectrode may include: a polysilicon layer doped with resistanceadjustment impurities; a polysilicon layer for adjusting grains, formedin the polysilicon layer doped with the resistance adjustment impuritiesand doped with grain adjustment impurities; an ohmic metal layer formedon the polysilicon layer including the polysilicon layer for adjustingthe grain; a barrier metal layer formed on the ohmic metal layer; and ametal layer formed on the barrier metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 is a schematic cross-sectional view for explaining an electrodestructure and a method of fabricating the electrode structure, accordingto an exemplary embodiment;

FIG. 2 is a schematic cross-sectional view of an electrode structure asa comparative example related to FIG. 1;

FIG. 3 is a schematic cross-sectional view for explaining an electrodestructure and a method of fabricating the electrode structure, accordingto another exemplary embodiment;

FIG. 4 is a schematic cross-sectional view for explaining an electrodestructure and a method of fabricating the electrode structure, accordingto another exemplary embodiment;

FIGS. 5 through 8 are schematic cross-sectional views for explaining asemiconductor device using an electrode structure and a method offabricating the semiconductor device, according to an exemplaryembodiment;

FIGS. 9 and 10 are schematic cross-sectional views for explaining asemiconductor device using an electrode structure and a method offabricating the semiconductor device, as a comparative example relatedto FIGS. 5 through 8;

FIG. 11 is a graph of variations in polysilicon grain size andpolysilicon resistivity with respect to concentrations of grainadjustment impurities doped in a polysilicon layer for adjusting grains,according to an exemplary embodiment;

FIG. 12 is a graph of variations in the thickness of a ohmic metal layerwith respect to concentrations of grain adjustment impurities doped in apolysilicon layer for adjusting grains, according to an exemplaryembodiment;

FIG. 13 is a graph of an X-ray graph of a polysilicon layer foradjusting grains with respect to concentrations of grain adjustmentimpurities, according to an exemplary embodiment;

FIG. 14 is a graph of variations of a leakage current with respect to agate voltage of a PMOS device, according to an exemplary embodiment;

FIG. 15 is a secondary ion mass spectrometry (SIMS) graph of diffusionof boron (B) that is impurities doped in a polysilicon layer, accordingto an exemplary embodiment;

FIG. 16 is a layout of a dynamic random access memory (DRAM) deviceusing an electrode structure, according to an exemplary embodiment;

FIGS. 17 and 18 are cross-sectional views of DRAM devices taken along aline Y-Y of FIG. 16, according to exemplary embodiments;

FIG. 19 is a plan view of a memory module including a semiconductordevice including an electrode structure, according to an exemplaryembodiment;

FIG. 20 is a schematic view of a memory card including a semiconductordevice including an electrode structure, according to an exemplaryembodiment; and

FIG. 21 is a schematic view of a system including a semiconductor deviceincluding an electrode structure, according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The disclosure will now be described more fully with reference to theaccompanying drawings, in which exemplary embodiments are shown. Theinventive concept may, however, be embodied in many different forms andshould not be construed as being limited to the embodiments set forthherein. Like reference numerals in the drawings denote like elements,and thus their description will be omitted. In the drawings, thethicknesses of layers and regions are exaggerated for clarity.

The terminology used herein is for describing particular embodimentsonly and is not intended to be limiting of exemplary embodiments. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, components, and/or groups thereof, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the present inventive concept.Further, the term “same” as used herein when referring to shapes, sizes,amounts, or other measures does not necessarily mean exactly the same,but is intended to encompass nearly identical measures within acceptablevariations that may occur, for example, due to manufacturing processes.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the figures. It will be understood thatthe spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

Embodiments are described herein with reference to cross-sectional orperspective illustrations that are schematic illustrations of idealizedembodiments (and intermediate structures). As such, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, embodimentsshould not be construed as limited to the particular shapes of regionsillustrated herein but are to include deviations in shapes that result,for example, from manufacturing. For example, an edge or corner regionillustrated as having sharp edges may have somewhat rounded or curvedfeatures. Likewise, elements illustrated as circular or spherical may beoval in shape or may have certain straight or flattened portions. Thus,the regions illustrated in the figures are schematic in nature and theirshapes as shown in the figures are not intended to limit the scope ofthe disclosed embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood in theart to which exemplary embodiments belong. It will be further understoodthat terms, such as those defined in commonly used dictionaries, shouldbe interpreted as having a meaning that is consistent with their meaningin the context of the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

First Embodiment of Electrode Structure and Method of Fabricating theElectrode Structure

FIG. 1 is a schematic cross-sectional view for explaining an electrodestructure 30-1 and a method of fabricating the electrode structure 30-1,according to an exemplary embodiment. FIG. 2 is a schematiccross-sectional view of an electrode structure 30 p-1 as a comparativeexample related to FIG. 1.

In more detail, the electrode structure 30-1 of the present embodimentand the electrode structure 30 p-1 of the comparative example will nowbe described. A gate insulation layer 10 is formed on a semiconductorsubstrate 100, for example, a silicon substrate. The electrodestructures 30-1 and 30 p-1 are formed on the gate insulation layer 10. Agate cap layer 22 is formed on the electrode structures 30-1 and 30 p-1.

In one embodiment, the electrode structure 30-1 includes a polysiliconlayer 12 doped with resistance adjustment impurities, a polysiliconlayer 14 for adjusting grains and doped with grain adjustmentimpurities, an ohmic metal layer 16, a barrier metal layer 18, and ametal layer 20 that are sequentially formed on the gate insulation layer10. In one embodiment, the polysilicon layer 14 for adjusting the grainis directly adjacent to the polysilicon layer 12 and is disposed betweenthe polysilicon layer 12 and the ohmic metal layer 16.

The polysilicon layer 14 for adjusting the grain includes impuritiesthat cause the grain size of grains in the polysilicon layer 14 to varycompared to the grain size of grains in the polysilicon layer 12. Forexample, in one embodiment, the polysilicon layers 12 and 14 include thesame polysilicon materials and the same resistance adjustmentimpurities, but the polysilicon layer 14 includes additional grainadjustment impurities that cause the grain size of grains in polysiliconlayer 14 to be on average smaller than the grain size of grains in thepolysilicon layer 12. The polysilicon layer 14 may be formed on thepolysilicon layer 12 doped with resistance adjustment impurities byin-situ depositing a precursor including grain adjustment impuritiesincluding, for example, one or more of carbon, nitrogen, and oxygen.When the grain adjustment impurities are carbon, for example, thepolysilicon layer 14 for adjusting the grain may be formed by in-situdepositing a precursor including SiH₃CH₃ and Si₂H₆ (or SiH₂Cl₂) or aprecursor including SiH₄ and C₂H₄ (or SiH₃CH₃). When the grainadjustment impurities are oxygen, for example, the polysilicon layer 14for adjusting the grain may be formed by in-situ depositing a precursorincluding N₃O and Si₂H₂ or a precursor including SiH₄ and N₂O. When thegrain adjustment impurities are nitrogen, for example, the polysiliconlayer 14 for adjusting the grain may be formed by in-situ depositing aprecursor including NH₃ and S₂H₆ or a precursor including SiH₄ and NH₃.Furthermore, the polysilicon layer 14 for adjusting the grain may bedoped with grain adjustment impurities while forming a polysilicon layerthrough an epitaxial growth process.

The polysilicon layer 14 for adjusting the grain may be formed byin-situ depositing a precursor including the grain adjustment impuritiesor through the epitaxial growth process so that the polysilicon layer 14for adjusting the grain is uniformly formed on the polysilicon layer 12doped with resistance adjustment impurities. The uniform forming of thepolysilicon layer 14 for adjusting the grain can improve the beneficialeffects of the disclosed embodiments.

The electrode structure 30 p-1 of the comparative example includes thepolysilicon layer 12 doped with resistance adjustment impurities, anohmic metal layer 16 a, the barrier metal layer 18, and the metal layer20 that are sequentially formed on the gate insulation layer 10. Theelectrode structure 30-1 further includes the polysilicon layer 14 foradjusting the grain, unlike the electrode structure 30 p-1 of thecomparative example.

Each of metal layer 20, barrier metal layer 18, and ohmic metal layers16 and 16 a may be referred to as metal material layers, and may includemetal material. For example, the metal material layers may include puremetals or metal alloys (e.g., copper, tungsten, titanium), or metalsilicides, metal nitrides, or other compounds that include metalelements. The metal layer 20 included in the electrode structures 30-1and 30 p-1 is used to reduce the resistance of the electrode structure30-1. The ohmic metal layers 16 and 16 a are used for an ohmic contactbetween a metal material layer and a semiconductor material layer, forexample, a polysilicon layer. The barrier metal layer 18 may have a highconductivity to maintain a highly conductive electrical contact betweenupper and lower metal material layers, and also serves a barrier todiffusion to prevent metal material from diffusing from the metal layer20 to the polysilicon material layers. As such, the barrier metal layer18 may comprise a metal material that is highly conductive and providesa low rate of diffusion, and may assist in isolating the metal layer 20from the polysilicon layers 12 and 14.

In one embodiment, the ohmic metal layers 16 and 16 a may include metalsilicide layers. The ohmic metal layers 16 and 16 a may include, forexample, tungsten layers, tungsten silicide layers, titanium layers,titanium nitride layers, cobalt layers, and nickel layers. The ohmicmetal layers 16 and 16 a may also include metal silicide layers, forexample, tungsten silicide layers. In one embodiment, the barrier metallayer 18 may include a titanium nitride layer. Metal layer 20 mayinclude, for example, tungsten, copper, or other pure metals, but alsomay include other conductive materials having low resistivity.

The resistance adjustment impurities doped in the polysilicon layer 12may include one or more of phosphorus (P), arsenic (As), and boron (B),for example. As described above, the electrode structure 30-1 furtherincludes the polysilicon layer 14 for adjusting the grain, in whichgrain adjustment impurities are precipitated among polysilicon grains.In one embodiment, the polysilicon layer 14 for adjusting the grain isdoped with one or more of carbon, nitrogen, and oxygen as grainadjustment impurities as mentioned above, in addition to the resistanceadjustment impurities such as phosphorus (P), arsenic (As), or boron(B). As such, the overall impurities in the polysilicon layer 14 aredifferent from the impurities in the polysilicon layer 12, and mayinclude the same impurities as in the polysilicon layer 12 (e.g., P, As,or B) as well as additional impurities not in the polysilicon layer 12(e.g., C, N, or O). The polysilicon layer 14 for adjusting the grain isdoped with grain adjustment impurities, and thus individual as well asaverage sizes of polysilicon grains in the polysilicon layer 14 may bereduced as compared to the grain sizes in polysilicon layer 12.

Therefore, as compared to the electrode structure 30 p-1 of thecomparative example, the electrode structure 30-1 of the presentembodiment can reduce the sizes of polysilicon grains included in thepolysilicon layer 14 for adjusting the grain, and precipitate the grainadjustment among polysilicon grains throughout the polysilicon layer 14.The thickness T01 of the ohmic metal layer 16 can be reduced byinhibiting a reaction between the polysilicon layer 14 for adjusting thegrain and the ohmic layer 16. This results from the use of the grainadjustment impurities in the polysilicon layer 14, and results in athinner ohmic metal layer than when a polysilicon layer without grainadjustment impurities is used. That is, the thickness T01 of the ohmicmetal layer 16 can be reduced by inhibiting agglomeration of materialsbetween the polysilicon layer 14 for adjusting the grain and the ohmiclayer 16.

The thickness T01 of the ohmic metal layer 16 of the electrode structure30-1 of the present embodiment may be smaller than a thickness T02 ofthe electrode structure 30 p-1 of the comparative example. However, theelectrode structure 30-1 of the present embodiment is not limited to thethickness T01 of the ohmic metal layer 16. In addition, the electrodestructure 30-1 of the present embodiment can reduce the thickness of thepolysilicon layer 12 and an interface resistance of the electrodestructure 30-1, compared to the electrode structure 30 p-1 of thecomparative example.

The polysilicon grains included in the polysilicon layer 14 foradjusting the grain have small sizes, resulting in a long diffusionpath, compared to the electrode structure 30 p-1 of the comparativeexample, and the grain adjustment impurities precipitated amongpolysilicon grains act as obstacles of the diffusion path. Thus, theelectrode structure 30-1 of the present embodiment can inhibit diffusionbetween metal atoms of the ohmic metal layer 16 and silicon atoms of thepolysilicon material layers, and can also inhibit the resistanceadjustment impurities included in the polysilicon layer 14 for adjustingthe grain, in particular, boron (B), from diffusing over to the gateinsulation layer 10.

Second Embodiment of Electrode Structure and Method of Fabricating theElectrode Structure

FIG. 3 is a schematic cross-sectional view for explaining an electrodestructure 30-2 and a method of fabricating the electrode structure 30-2,according to another exemplary embodiment.

Specifically, the electrode structure 30-2 of the present embodiment isthe same as the electrode structure 30-1 of the previous embodiment,except that the polysilicon layer 14 for adjusting the grain is disposedbetween a first polysilicon layer 12 a and a second polysilicon layer 12b. The electrode structure 30-2 of the present embodiment includes thefirst polysilicon layer 12 a doped with resistance adjustmentimpurities, the polysilicon layer 14 for adjusting the grain and dopedwith grain adjustment impurities, the second polysilicon layer 12 bdoped with resistance adjustment impurities, the ohmic metal layer 16,the barrier metal layer 18, and the metal layer 20 that are sequentiallyformed on the gate insulation layer 10. In one embodiment, both firstand second polysilicon layers 12 a and 12 b include the same resistanceadjustment impurities, and polysilicon layer 14 includes the resistanceadjustment impurities as well as additional grain adjustment impurities.

The polysilicon layer 14 for adjusting the grain included in theelectrode structure 30-2 of the present embodiment may be formed in aspecific level of the first polysilicon layer 12 a and the secondpolysilicon layer 12 b. In particular, in one embodiment, thepolysilicon layer 14 for adjusting the grain is formed by depositing aprecursor including grain adjustment impurities or through an epitaxialgrowth process so that the polysilicon layer 14 for adjusting the grainis uniformly formed between the first polysilicon layer 12 a and thesecond polysilicon layer 12 b. The uniformly forming of the polysiliconlayer 14 for adjusting the grain can improve the effect of the presentembodiments.

When the polysilicon layer 14 for adjusting the grain is disposedbetween the first polysilicon layer 12 a and the second polysiliconlayer 12 b, polysilicon grains included in the polysilicon layer 14 foradjusting the grain have smaller sizes and higher concentration,compared to the electrode structure 30 p-1 of the comparative example,resulting in a long diffusion path, and grain adjustment impuritiesprecipitated among polysilicon grains act as obstacles of the diffusionpath. Thus, the electrode structure 30-2 of the present embodiment caninhibit diffusion between metal atoms of the ohmic metal layer 16 andsilicon atoms of the polysilicon material layers, and can also inhibitthe resistance adjustment impurities included in the polysilicon layer14 for adjusting the grain and the second polysilicon layer 12 b, inparticular, boron (B), from diffusing over to the gate insulation layer10.

Third Embodiment of Electrode Structure and Method of Fabricating theElectrode Structure

FIG. 4 is a schematic cross-sectional view for explaining an electrodestructure 30-3 and a method of fabricating the electrode structure 30-3,according to another exemplary embodiment.

Specifically, the electrode structure 30-3 of the present embodiment isthe same as the electrode structure 30-1 of the previous embodiment,except that the polysilicon layer 14 for adjusting the grain is formedin the entire polysilicon layer 12. That is, the electrode structure30-3 of the present embodiment is the same as the electrode structure30-1 of the previous embodiment, except that a single polysilicon layer24 including the polysilicon layer 14 for adjusting the grain and dopedwith grain adjustment impurities and the polysilicon layer 12 doped withresistance adjustment impurities is formed.

The electrode structure 30-3 of the present embodiment includes thesingle polysilicon layer 24 including the polysilicon layer 14 foradjusting the grain and doped with grain adjustment impurities and thepolysilicon layer 12 doped with resistance adjustment impurities, theohmic metal layer 16, the barrier metal layer 18, and the metal layer 20that are sequentially formed on the gate insulation layer 10. In thiscase, as compared to the electrode structure 30 p-1 of the comparativeexample, the thickness of the ohmic layer 16 of the electrode structure30-3 of the present embodiment is reduced, thereby reducing thethickness of the single polysilicon layer 24, and inhibiting theresistance adjustment impurities, in particular, boron (B), fromdiffusing over to the gate insulation layer 10.

Next, a semiconductor device using the electrode structures 30-1, 30-2,and 30-3 of the above embodiments, for example, a complementarymetal-oxide-semiconductor (CMOS) device, will now be described. Inaddition, a method of fabricating the electrode structures 30-1, 30-2,and 30-3 and a method of fabricating the semiconductor device will nowbe described. The electrode structures 30-1, 30-2, and 30-3 are labeledas an electrode structure 30 for descriptive convenience.

FIGS. 5 through 8 are schematic cross-sectional views for explaining asemiconductor device using an electrode structure and a method offabricating the semiconductor device, according to exemplaryembodiments.

Referring to FIG. 5, a device isolation layer 102 is formed on asemiconductor substrate 100 including an n-typemetal-oxide-semiconductor (NMOS) region N and a p-typemetal-oxide-semiconductor (PMOS) region P. The device isolation layer102 may be formed through, for example, a shallow trench isolation (STI)process. An NMOS active region and a PMOS active region are defined bythe NMOS region N and the PMOS region P, respectively, by the deviceisolation layer 102. A P-well and an N-well may be formed in the NMOSactive region and the PMOS active region, respectively, through aprocess of forming a CMOS well.

Gate insulation material layers 106 a and 106 b are formed on the entiresurface of the semiconductor device 100 including the device isolationlayer 102. The gate insulation material layers 106 a and 106 b mayinclude, for example, silicon oxide layers, silicon oxynitride layers orhigh dielectric layers. High dielectric layers may include, for example,aluminium oxide layers, hafnium oxide layers, zirconium oxide layers,lantanium oxide layers, hafnium silicate layers, hafnium aluminium oxidelayers, titanium oxide layers, or tantalum oxide layers, or depositionlayers including combinations thereof. The gate insulation materiallayers 106 a and 106 b may be deposited, for example, through chemicalvapor deposition (CVD) or atomic layer deposition (ALD) or may be grownthrough a thermal oxidation.

Polysilicon material layers 108 a and 108 b doped with resistanceadjustment impurities, for example, phosphorus (P), arsenic (As), orboron (B), are formed on the gate insulation material layers 106 a and106 b. In one embodiment, the polysilicon material layer 108 a dopedwith boron (B) is formed in the PMOS region P. In addition, thepolysilicon material layer 108 b doped with phosphorus (P) or arsenic(As) is formed in the NMOS region N. Polysilicon material layers 110 aand 110 b for adjusting grains and doped with grain adjustmentimpurities are formed on the polysilicon material layers 108 a and 108 bdoped with resistance adjustment impurities.

The polysilicon material layers 110 a and 110 b for adjusting the grainare doped with any one of carbon, nitrogen, and oxygen as grainadjustment impurities, in addition to phosphorus (P), arsenic (As), orboron (B) as resistance adjustment impurities.

The polysilicon material layers 110 a and 110 b for adjusting the grainmay be formed on the polysilicon material layers 108 a and 108 b dopedwith resistance adjustment impurities by in-situ depositing a precursorincluding grain adjustment impurities, for example, any one of carbon,nitrogen, and oxygen. The polysilicon material layers 110 a and 110 bfor adjusting the grain may be formed by doping any one of carbon,nitrogen, and oxygen through an epitaxial growth process.

The polysilicon material layers 110 a and 110 b for adjusting the grainare doped with grain adjustment impurities as mentioned above, and thussizes of polysilicon grains may be reduced.

Referring to FIG. 6, ohmic metal layers 112 a and 112 b, barrier metallayers 114 a and 114 b, and metal layers 116 a and 116 b are formed onthe polysilicon material layers 110 a and 110 b for adjusting the grain.The ohmic metal layers 112 a and 112 b may include, for example,tungsten layers, tungsten silicide layers, titanium layers, titaniumnitride layers, cobalt layers, and nickel layers. The barrier metallayers 114 a and 114 b may include, for example, titanium nitridelayers. The metal layers 116 a and 116 b may include, for example,tungsten or copper layers.

A difference in the thickness between the ohmic metal layer 112 b of theNMOS region N and the ohmic metal layer 112 a of the PMOS region P maybe reduced by using the polysilicon material layers 110 a and 110 b foradjusting the grain, compared to a situation where the a grain adjustinglayer is not used. That is, if a subsequent thermal process is performedafter the ohmic metal layers 112 a and 112 b are formed, the grainadjustment impurities, for example, any one of carbon, nitrogen, andoxygen, inhibit diffusion between metal atoms of the ohmic metal layers112 a and 112 b and silicon atoms of the polysilicon material layers 110a and 110 b for adjusting the grain or the polysilicon material layers108 a and 108 b, thereby reducing the difference in the thicknessbetween the ohmic metal layer 112 a and the ohmic metal layer 112 b.

Further, if a subsequent thermal process is performed after the ohmicmetal layers 112 a and 112 b are formed, the grain adjustment impuritiesinhibit agglomeration between the polysilicon material layers 110 a and110 b for adjusting the grain and the ohmic metal layers 112 a and 112 band prevent an increase in the interface resistance of the electrodestructure.

Further, the grain adjustment impurities included in the polysiliconmaterial layers 110 a and 110 b for adjusting the grain of the presentembodiment can reduce sizes of polysilicon grains. Thus, when asubsequent thermal process is performed after the ohmic metal layers 112a and 112 b are formed, the interface characteristics of the gateinsulation material layers 106 a and 106 b can be improved by inhibitingdiffusion of the resistance adjustment impurities included in thepolysilicon material layers 110 a and 110 b for adjusting the grain, inparticular, boron (B).

Referring to FIG. 7, mask layers 118 a and 118 b are formed on the metallayers 116 a and 116 b of the PMOS region P and the NMOS region N,respectively. The mask layers 118 a and 118 b may include, for example,silicon nitride layers. The mask layers 118 a and 118 b may be used asgate cap layers.

Referring to FIG. 8, the metal layers 116 a and 116 b, the barrier metallayers 114 a and 114 b, the ohmic metal layers 112 a and 112 b, thepolysilicon layers 110 a and 110 b for adjusting the grain, thepolysilicon layers 108 a and 108 b, and the gate insulation layers 106 aand 106 b are sequentially etched by using the mask layers 118 a and 118b as etching masks. In one embodiment, a plasma dry etching process maybe used.

As a result, a first gate stack 160 including a first gate insulationlayer 120 a, a first electrode structure 30-4, and a first gate caplayer 118 a is formed on the PMOS region P. The first electrodestructure 30-4 includes a metal layer 130 a, a barrier metal layer 128a, an ohmic metal layer 126 a, a polysilicon layer for adjusting grains124 a, and a polysilicon layer 122 a. A second gate stack 170 includinga second gate insulation layer 120 b, a second electrode structure 30-5,and a second gate cap layer 118 b is formed on the NMOS region N. Thesecond electrode structure 30-5 includes a metal layer 130 b, a barriermetal layer 128 b, an ohmic metal layer 126 b, a polysilicon layer foradjusting grains 124 b, and a polysilicon layer 122 b. A surface of thesemiconductor substrate 100 is exposed between the first and second gatestacks 160 and 170.

During the etching process, the thickness TP1 of the polysilicon layer122 a and the polysilicon layer for adjusting the grain 124 a includedin the first electrode structure 30-4 and the thickness TP2 of thepolysilicon layer 122 b and the polysilicon layer for adjusting grains124 b included in the second electrode structure 30-5 do not differ fromeach other, and the thicknesses of the polysilicon layer 122 a and 122 band the polysilicon layers for adjusting the grain 124 a and 124 b maybe reduced.

Next, a P type impurity region 132 is formed by injecting P typeimpurities, for example, boron (B), into both sides of the first gatestack 160 of the PMOS region P. The P type impurity region 132 is a Ptype source/drain region. An N type impurity region 134 is formed byinjecting N type impurities, for example, phosphorus (P) or arsenic(As), into both sides of the second gate stack 170 of the NMOS region N.The N type impurity region 134 is an N type source/drain region.

FIGS. 9 and 10 are schematic cross-sectional views for explaining asemiconductor device using an electrode structure and a method offabricating the semiconductor device as a comparative example related toFIGS. 5 through 8.

Specifically, the semiconductor device of the comparative example is thesame as the semiconductor device described with reference to FIGS. 5through 8, except that a polysilicon layer for adjusting grains is notformed. FIG. 9 corresponds to FIGS. 6 and 7. The device isolation layer102 is formed in the semiconductor substrate 100 including the NMOSregion N and the PMOS region P. The gate insulation material layers 106a and 106 b and the polysilicon material layers 108 a and 108 b dopedwith resistance adjustment impurities, for example, phosphorus (P),arsenic (As), or boron (B), are formed on the semiconductor layer 100.

Thereafter, ohmic metal layers 140 a and 140 b, the barrier metal layers114 a and 114 b, and the metal layers 116 a and 116 b are formed on thepolysilicon layers 108 a and 108 b. The ohmic metal layers 140 a and 140b may include, for example, tungsten layers, tungsten silicide layers,titanium layers, titanium nitride layers, cobalt layers, and nickellayers. The materials of the barrier metal layers 114 a and 114 b andthe metal layers 116 a and 116 b may be the same as described above.

If a subsequent thermal process is performed after the ohmic metallayers 140 a and 140 b are formed, a reaction between the ohmic metallayer 140 b of the NMOS region N and the polysilicon material layer 108b is different from that between the ohmic metal layer 140 a of the PMOSregion P and the polysilicon material layer 108 a. Thus, the thicknessof the ohmic metal layer 140 b of the NMOS region N may be greater thanthat of the ohmic metal layer 140 a of the PMOS region P.

In other words, the thicknesses of the ohmic metal layer 140 b of theNMOS region N and the ohmic metal layer 140 a of the PMOS region Pdiffer from each other. Such a difference in the thickness makes itdifficult to reliably perform a subsequent stack process in thecomparative example, unlike the disclosed embodiments, which help evenlyreduce the depth of a gate stack throughout a semiconductor device.

Further, if a subsequent thermal process is performed after the ohmicmetal layers 140 a and 140 b are formed, significant agglomerationbetween the ohmic metal layers 140 a and 140 b and the polysiliconmaterial layers 108 a and 108 b occurs, which increases the interfaceresistance of the electrode structure.

If a subsequent thermal process is performed after the ohmic metallayers 140 a and 140 b are formed, resistance adjustment impuritiesincluded in the polysilicon layers 108 a and 108 b, in particular, boron(B), diffuse relatively easily over to a gate insulation layer, whichdeteriorates the interface characteristics of the gate insulation layer.In the same manner as described above in connection with FIG. 8, themask layers 118 a and 118 b are formed on the metal layers 116 a and 116b of the PMOS region P and the NMOS region N, respectively.

Referring to FIG. 10, the metal layers 116 a and 116 b, the barriermetal layers 114 a and 114 b, the ohmic metal layers 140 a and 140 b,the polysilicon layers 108 a and 108 b, and the gate insulation layers106 a and 106 b are sequentially etched by using the mask layers 118 aand 118 b as etching masks.

A first gate stack 160 p including the first gate insulation layer 120a, a first comparative electrode structure 30 p-2, and the first gatecap layer 118 a is formed on the PMOS region P. The first comparativeelectrode structure 30 p-2 includes the metal layer 130 a, the barriermetal layer 128 a, the ohmic metal layer 142 a, and the polysiliconlayer 122 a. A second gate stack 170 p including the second gateinsulation layer 120 b, a second comparative electrode structure 30 p-3,and the second gate cap layer 118 b is formed on the NMOS region N. Thesecond comparative electrode structure 30 p-3 includes the metal layer130 b, the barrier metal layer 128 b, the ohmic metal layer 142 b, andthe polysilicon layer 122 b. A surface of the semiconductor substrate100 is exposed between the first and second gate stacks 160 p and 170 p.

In the comparative example, the thickness T03 of the ohmic metal layer142 a included in the first comparative electrode structure 30 p-2 andthe thickness T04 of the ohmic metal layer 142 b included in the secondcomparative electrode structure 30 p-3 differ from each other, and thusthe thickness TP3 of the polysilicon layer 122 a included in the firstcomparative electrode structure 30 p-2 and the thickness TP4 of thepolysilicon layer 122 b included in the second comparative electrodestructure 30 p-3 also differ from each other.

In the comparative example, when the first and second comparativeelectrode structures 30 p-2 and 30 p-3 are formed during an etchingprocess, a difference in the thickness between the polysilicon layers122 a and 122 b causes pitting 150 which is indentations in thesemiconductor substrate 100 of the NMOS region N. Thus, unlike thedisclosed embodiments, it is difficult to reliably perform a subsequentstack process in the comparative example.

Next, the P type impurity region 132 is formed in both sides of thefirst comparative gate stack 160 p of the PMOS region P. The N typeimpurity region 134 is formed in both sides of the second comparativegate stack 170 p of the NMOS region N.

FIG. 11 is a graph of variations of polysilicon grain size GS andpolysilicon resistivity R with respect to concentrations of grainadjustment impurities doped in a polysilicon layer for adjusting thegrain, according to an exemplary embodiment.

Specifically, as described above, an electrode structure as disclosedherein includes the polysilicon layer for adjusting the grain doped withthe grain adjustment impurities. Referring to the example shown in FIG.11, the grain adjustment impurities use carbon. The higher theconcentration (%) of a carbon atom, the smaller the size GS of thepolysilicon grain, and the greater the resistivity R. As shown in FIG.11, in one embodiment, as a result of the grain adjustment impuritiesreaching a certain percentage, an average grain size of grains in thepolysilicon layer for adjusting grains may be less than a certainpercentage (e.g., 33%, or 20%) of the average grain size of grains inthe polysilicon layer with resistance adjustment impurities (e.g.,compare the grain size at 0% impurity concentration with the grain sizeat 2% impurity concentration or at 4% impurity concentration, as shownin FIG. 11).

The grain adjustment impurities are dopants which reduce the size GS ofthe polysilicon grain, thereby obtaining various effects as describedabove. For example, a reduction in the size GS of the polysilicon graininhibits agglomeration between the polysilicon layer and an ohmic metallayer, thereby reducing the interface resistance of the electrodestructure and a difference in the thickness between the ohmic layers ofan NMOS region and a PMOS region. Furthermore, resistance adjustmentimpurities included in the polysilicon layer for adjusting the grain, inparticular, boron (B), are inhibited from diffusing over to a gateinsulation layer, thereby improving the interface characteristics of thegate insulation layer.

FIG. 12 is a graph of variations of the thickness of a ohmic metal layerwith respect to concentrations of grain adjustment impurities doped in apolysilicon layer for adjusting the grain, according to an exemplaryembodiment.

Specifically, as described above, an electrode structure includes thepolysilicon layer for adjusting the grain doped with the grainadjustment impurities. Referring to the example of FIG. 12, the grainadjustment impurities use carbon, and an ohmic metal layer uses atungsten silicide layer. The higher the concentration (%) of a carbonatom, the smaller the thickness of the tungsten silicide layer that isthe ohmic metal layer. For example, in one embodiment, as a result ofthe grain adjustment impurities, a thickness of the ohmic metal layercan be reduced by more than 25% compared to if the grain adjustmentimpurities had not been included the polysilicon layer (e.g., comparethe thickness at 0.0% impurity concentration to the thickness at 2.2%impurity concentration).

As described above, the grain adjustment impurities are dopants whichreduce the size of the polysilicon grain, thereby inhibitingagglomeration between the polysilicon layer and the ohmic metal layer. Areduction in the thickness of the ohmic metal layer may reduce theinterface resistance of the electrode structure.

FIG. 13 is a graph of an X-ray graph of a polysilicon layer foradjusting grains with respect to concentrations of grain adjustmentimpurities, according to an exemplary embodiment.

Specifically, an electrode structure as disclosed herein includes thepolysilicon layer for adjusting the grain, which is doped with grainadjustment impurities. Referring to the example of FIG. 13, the grainadjustment impurities use carbon. The higher the concentration (%) of acarbon atom (e.g., compare 0.4%, 2.2%, and 4%), the smaller the size ofthe polysilicon grain, and the lower the peak intensity of diffractionfor the different diffraction angles of polysilicon grain. The grainadjustment impurities are dopants that reduce the size of thepolysilicon grain, thereby obtaining various beneficial effects of theas described above.

FIG. 14 is a graph of variations of a leakage current with respect to agate voltage Vg of a PMOS device, according to an exemplary embodiment.

Specifically, the graph shows variations of the leakage current withrespect to the gate voltage Vg of the PMOS device including an electrodestructure of the disclosed embodiments. The PMOS device is formed in thePMOS region P of FIG. 8. The electrode structure includes a polysiliconlayer for adjusting grains doped with grain adjustment impurities.

Referring to the example of FIG. 14, the grain adjustment impurities usecarbon. The leakage current of the disclosed embodiments is low comparedto the PMOS device P of the comparative example that does not includethe polysilicon layer for adjusting the grain doped with grainadjustment impurities. That results in part from the polysilicon layerfor adjusting the grain inhibiting boron (B) or other dopants of thepolysilicon layer from diffusing.

FIG. 15 is a secondary ion mass spectrometry (SIMS) graph of diffusionof boron (B) that is impurities doped in a polysilicon layer, accordingto an exemplary embodiment.

Specifically, reference character I indicates a measurement of thediffusion of boron (B) of a sample of the disclosed embodiments in whichthe polysilicon layer doped with carbon as the grain adjustmentimpurities is formed after a gate oxide layer is formed on asemiconductor substrate as a gate insulation layer. Reference characterP indicates a measurement of the diffusion of boron (B) in a sample of acomparative example in which a polysilicon layer not doped with carbonis formed after a gate oxide layer is formed on a semiconductorsubstrate as a gate insulation layer.

Referring to FIG. 15, in the sample of the embodiment in which apolysilicon layer, the gate oxide layer, and the polysilicon layer dopedwith carbon on a semiconductor substrate are formed, boron (B) has a lowconcentration. This means that the diffusion of boron (B) is inhibitedwhen the polysilicon layer is doped with carbon.

An integrated circuit semiconductor device, for example, a dynamicrandom access memory (DRAM) device, using the electrode structure 30 ofthe disclosed embodiments will now be described. However, the electrodestructure 30 can be used in other memory devices (e.g., PRAM, SRAM,flash memory, etc.) or non-memory devices as well.

FIG. 16 is a layout of a DRAM device using an electrode structure,according to an exemplary embodiment. However, the disclosed embodimentsare not limited to this exemplary layout of the DRAM device.

Active regions AR are defined by non-active regions (field regions(FR)). Two word lines W/L cross each of the active regions AR. Bit linesB/L are disposed in different layers to those of the word lines W/L andare perpendicular to the word lines W/L. The word lines W/L are disposedin a direction, and the bit lines B/L are disposed perpendicular to theword lines W/L.

Direct contact (DC) pad electrodes I connected to the bit lines B/L areformed on drain regions disposed in the active regions AR. Buriedcontact (BC) pad electrodes II connected to lower electrodes are formedon source regions disposed in the active regions AR. Capacitors CA ofthe DRAM device, i.e. the lower electrodes, are formed on the BC padelectrodes II.

FIGS. 17 and 18 are exemplary cross-sectional views of DRAM devices,taken along a line Y-Y of FIG. 16.

Referring to FIG. 17, in one embodiment, the DRAM device includes aplanar channel array transistor. Referring to FIG. 18, in oneembodiment, the DRAM device includes a recess channel array transistor.

The active region AR defined by the non-active regions FR is formed onthe semiconductor substrate 100, for example, a silicon substrate. Thenon-active regions FR are formed by burying an insulation layer intrenches 202 formed by etching the semiconductor substrate 100. Linerlayers 203, for example, nitride layers, may be formed in the trenches202.

A plurality of gate stacks 214 that act as the word lines W/L are formedon the semiconductor substrate 100 in which the active region AR isdefined. Each gate stack 214 includes a gate insulation layer 206, agate electrode 208, which may include the electrode structure 30, a gatecap layer 210, and a gate spacer 212. In FIG. 18, the recess type gatestack 214 includes the gate insulation layer 206 formed in the innerwall of a recess channel trench 205, a gate electrode 208 burying therecess channel trench 205 and including the electrode structure 30, andthe gate cap layer 210 and the gate spacer 212 formed on the gateelectrode 208.

The gate stacks 214 may include the electrode structure 30 as describedabove. The construction and function of the electrode structure 30 aredescribed above and thus a detailed description thereof will not berepeated here. In one embodiment, the gate cap layer 210 includes asilicon nitride layer having a good selection ratio with a silicon oxidelayer used as an interlayer insulation layer. The gate spacer 212 mayinclude a silicon nitride layer having a good selection ratio with asilicon oxide layer used as an interlayer insulation layer.

Impurity regions 216 and 218, i.e. the source region 216 and the drainregion 218, are formed in the lower portions of both walls of the gatestacks 214. The impurity regions 216 and 218 are formed on thesemiconductor substrate 100 between the gate stacks 214.

In one embodiment, contact pad electrodes 220 and 222, which may includethe electrode structure 30, are formed on the semiconductor substrate100 between the gate spacers 212. The construction and function of theseelectrode structures 30 are described above and thus a detaileddescription thereof will not be repeated here. When the contact padelectrodes 220 and 222 include the electrode structure 30, impuritiesincluded in the electrode structure 30 are prevented from diffusing overto the impurity regions 216 and 218, i.e. the source region 216 and thedrain region 218, thereby improving the electrical characteristics ofthe electrode structure 30, and no void or seam is formed in the contactpad electrodes 220 and 222, thereby improving the contactcharacteristics of the electrode structure 30.

The contact pad electrodes 220 and 222 are formed between the gatestacks 214 on the impurity regions 216 and 218. In one embodiment, thecontact pad electrodes 220 and 222 are insulated by an interlayerinsulation layer 224. The interlayer insulation layer 224 includes, forexample, a silicon oxide layer. The contact pad electrodes 220 and 222respectively include the DC pad electrode 222 and the BC pad electrode220 as described above. The bit line B/L and the capacitors CA areconnected to the DC pad electrode 222 and the BC pad electrode 220,respectively.

FIG. 19 is a plan view of a memory module 1000 including a semiconductordevice including an electrode structure, according to an exemplaryembodiment.

In one embodiment, the memory module 1000 may include a printed circuitboard (PCB) 1100 and a plurality of semiconductor packages 1200. Thesemiconductor packages 1200 may include the semiconductor deviceincluding the electrode structure according to the disclosedembodiments. The semiconductor packages 1200 may include, for example, aplurality of stacked semiconductor devices, or a single semiconductordevice, or may include a package-on-package device. The memory module1000 may be a single in-line memory module (SIMM) in which thesemiconductor packages 1200 are mounted on one surface of the PCB 1100,or a dual in-line memory module (DIMM) in which the semiconductorpackages 1200 are arranged in both surfaces of the PCB 1100.Furthermore, the memory module 1000 may be a fully buffered DIMM(FBDIMM) including an advanced memory buffer (AMB) that providesexternal signals to each of the semiconductor packages 1200.

FIG. 20 is a schematic view of a memory card 2000 including asemiconductor device including an electrode structure, according to anexemplary embodiment.

Specifically, the memory card 2000 may be disposed in such a way that acontroller 2100 and a memory 2200 can exchange electrical signals. Forexample, if the controller 2100 sends a command to the memory 2200, thememory 2200 can transmit data.

The memory 2200 may include the semiconductor device including theelectrode structure according to the various disclosed embodiments.

The memory card 2000 may include various types of memory cards, forexample, a memory stick card, a smart media card (SM), a secure digitalcard (SD), a mini-secure digital card (mini SD), a multimedia card(MMC), and the like.

FIG. 21 is a schematic view of a system 3000 including a semiconductordevice including an electrode structure, according to an exemplaryembodiment.

Specifically, the system 3000 may communicate data using a processor3100, a memory 3200, an input/output device 3300, and a bus 3400. Thememory 3200 of the system 3000 may include, for example, a random accessmemory (RAM) and a read only memory (ROM). The system 300 may furtherinclude a peripheral device 3500 such as a floppy disk drive or acompact disk (CD) ROM drive.

The memory 3200 may include the semiconductor device including theelectrode structure according to the disclosed embodiments.

The memory 3200 may store a code and data for operating the processor3100. The system 3000 may be used, for example, in a mobile phone, anMP3 player, a navigation system, a portable multimedia player (PMP), asolid state disk (SSD), or a household appliance.

While the inventive concept has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodthat various changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

1. An electrode structure comprising: a first polysilicon layer dopedwith resistance adjustment impurities; a second polysilicon layer foradjusting grains, formed in the first polysilicon layer doped with theresistance adjustment impurities and additionally doped with grainadjustment impurities; an ohmic metal layer formed on the first andsecond polysilicon layers; a barrier metal layer formed on the ohmicmetal layer; and a metal layer formed on the barrier metal layer.
 2. Theelectrode structure of claim 1, wherein the second polysilicon layer isdisposed between the first polysilicon layer and the ohmic metal layer.3. The electrode structure of claim 2, wherein the second polysiliconlayer is uniformly formed on the first polysilicon layer.
 4. Theelectrode structure of claim 1, wherein the second polysilicon layer isformed in a specific level of the first polysilicon layer.
 5. Theelectrode structure of claim 4, wherein the second polysilicon layer isuniformly formed in the first polysilicon layer.
 6. The electrodestructure of claim 1, wherein the second polysilicon layer is formed inthe entire first polysilicon layer so that the second polysilicon layerand the first polysilicon are formed as a single polysilicon layer. 7.The electrode structure of claim 1, wherein the grain adjustmentimpurities doped in the second polysilicon layer include one or more ofcarbon, nitrogen, and oxygen.
 8. The electrode structure of claim 1,wherein the ohmic metal layer is a metal silicide layer.
 9. Theelectrode structure of claim 1, wherein the grain adjustment impuritiesare a different type of impurity from the resistance adjustmentimpurities.
 10. The electrode structure of claim 1, wherein a grain sizeof grains in the second polysilicon layer is smaller than a grain sizeof grains in the first polysilicon layer.
 11. The electrode structure ofclaim 1, wherein, as a result of the grain adjustment impurities, anaverage grain size of grains in the second polysilicon layer is lessthan 50% of the average grain size of grains in the first polysiliconlayer.
 12. The electrode structure of claim 1, wherein, as a result ofthe grain adjustment impurities, a thickness of the ohmic metal layer isreduced by at least 25% compared to if the grain adjustment impuritieshad not been included in the second polysilicon layer. 13-33. (canceled)34. An electrode structure for a semiconductor device, the electrodestructure comprising: a first polysilicon layer disposed on aninsulating layer, the first polysilicon layer including resistanceadjustment impurities; a second polysilicon layer disposed on the firstpolysilicon layer, the second polysilicon layer including the resistanceadjustment impurities and additional grain adjustment impurities,wherein the resistance adjustment impurities are a different type ofimpurity from the grain adjustment impurities, and wherein the secondpolysilicon layer has a higher grain concentration than the firstpolysilicon layer; and one or more metal layers formed on the secondpolysilicon layer, wherein the first polysilicon layer is disposedbetween the insulating layer and the second polysilicon layer, and thesecond polysilicon layer is disposed between the first polysilicon layerand the one or more metal layers.
 35. The electrode structure of claim34, wherein the one or more metal layers include: an ohmic metal layerformed on the second polysilicon layer; a barrier metal layer formed onthe ohmic metal layer, such that the ohmic metal layer is disposedbetween the second polysilicon layer and the barrier metal layer; and ametal layer formed on the barrier metal layer, such that the barriermetal layer is disposed between the ohmic metal layer and the metallayer.
 36. The electrode structure of claim 34, wherein: the resistanceadjustment impurities include one or more of carbon, nitrogen, andoxygen.
 37. The electrode structure of claim 36, wherein: the grainadjustment impurities include one or more of phosphorus, arsenic, orboron.
 38. The electrode structure of claim 34, wherein: the electrodestructure is part of a first gate disposed on an N-doped region of thesemiconductor device.
 39. The electrode structure of claim 38, furthercomprising: a second gate of the semiconductor device, the second gateincluding an additional electrode structure, the additional electrodestructure including a respective first semiconductor layer, secondsemiconductor layer, and one or more metal layers corresponding to therespective layers of the electrode structure of the first gate, whereinthe second gate is disposed on a P-doped region of the semiconductordevice, and wherein the thicknesses of the layers of the electrodestructure of the second gate are the same as respective thicknesses ofthe respective layers of the electrode structure of the first gate. 40.An electrode structure for a semiconductor device, the electrodestructure comprising: a first polysilicon layer disposed on aninsulating layer, the first polysilicon layer including first impuritieshaving a first impurity concentration; a second polysilicon layerdisposed on the first polysilicon layer, the second polysilicon layerincluding second impurities having a second impurity concentrationhigher than the first impurity concentration; and one or more metallayers formed on the second polysilicon layer, wherein the firstpolysilicon layer is disposed between the insulating layer and thesecond polysilicon layer, and the second polysilicon layer is disposedbetween the first polysilicon layer and the one or more metal layers.41. The electrode structure of claim 40, wherein the first polysiliconlayer is directly adjacent to the second polysilicon layer.
 42. Theelectrode structure of claim 40, further comprising: a third polysiliconlayer disposed between the first polysilicon layer and the insulatinglayer and having the same impurity concentration as the secondpolysilicon layer.
 43. The electrode structure of claim 40, wherein: thesecond impurities include the first impurities and additionalimpurities.
 44. The electrode structure of claim 43, wherein: the firstimpurities include one or more of carbon, nitrogen, and oxygen; and theadditional impurities include one or more of phosphorus, arsenic, andboron.
 45. The electrode structure of claim 40, wherein: the secondpolysilicon layer has a lower grain size than the first polysiliconlayer.
 46. The electrode structure of claim 40, wherein the one or moremetal layers include: an ohmic metal layer formed on the secondpolysilicon layer; a barrier metal layer formed on the ohmic metallayer, such that the ohmic metal layer is disposed between the secondpolysilicon layer and the barrier metal layer; and a metal layer formedon the barrier metal layer, such that the barrier metal layer isdisposed between the ohmic metal layer and the metal layer.